Bahasa takrifan perkakasan
Daripada Wikipedia, ensiklopedia bebas.
Dalam bidang elektronik, sebuah bahasa takrifan perkakasan (HDL, sing. Hardware Description Language) adalah mana-mana bahasa daripada kelas bahasa komputer untuk pentakrifan rasmi litar elektronik. Ia boleh mengtakrifkan pengendalian litar, rekaannya dan pertubuhan, dan ujian untuk mempastikan pengendaliannya dengan kaedah simulasi.
Isi kandungan |
Bahasa [sunting]
Reka bentuk litar analog [sunting]
| Singkatan | Nama | Catatan |
|---|---|---|
| AHDL | Analog Hardware Descriptive Language (HDL) | bahasa takrifan perkakasan analog terbuka |
| SpectreHDL | SpectreHDL | bahasa taksiran perkakasan berhak milik |
| Verilog-AMS | Verilog for Analog and Mixed-Signal | an open standard extending Verilog for analog and mixed analog/digital simulation |
| HDL-ATM | HDL-A | bahasa takrifan perkakasan analog berhak milik |
Reka bentuk litar digital [sunting]
| Singkatan | Nama | Catatan |
|---|---|---|
| ABEL | Advanced Boolean Expression Language | |
| AHDL | Altera HDL | a proprietary language from Altera |
| AHPL | A Hardware Programing language | |
| Bluespec | high-level HDL originally based on Haskell, now with a SystemVerilog syntax | |
| C-to-Verilog | Converter from C to Verilog | |
| Confluence | a functional HDL; has been discontinued | |
| CoWareC | a C-based HDL by CoWare. Now discontinued in favor of SystemC | |
| CUPL | Universal Compiler for Programmable Logic [1] | a proprietary language from Logical Devices, Inc. |
| ELLA | no longer in common use | |
| ESys.net | .net framework written in C# | |
| Handel-C | a C-like design language | |
| HJJ | Hardware Join Java | based on Join Java |
| HML | based on SML | |
| Hydra | berasaskan Haskell | |
| Impulse C | satu lagi HDL ala C | |
| ParC | Parallel C++ | C++ extended with HDL style threading and communication for task-parallel programming |
| JHDL | berasaskan Java | |
| Lava | berasaskan Haskell | |
| Lola | a simple language used for teaching | |
| M | HDL daripda Mentor Graphics | |
| MyHDL | berasaskan Python | |
| PALASM | untuk peranti Programmable Array Logic (PAL) | |
| ROCCC 2.0 | Riverside Optimizing Compiler for Configurable Computing | Free and open-source C to HDL tool |
| RHDL | based on the Ruby programming language | |
| Ruby (hardware description language) | ||
| SystemC | a standardized class of C++ libraries for high-level behavioral and transaction modeling of digital hardware at a high level of abstraction, i.e. system-level | |
| SystemVerilog | a superset of Verilog, with enhancements to address system-level design and verification | |
| SystemTCL | SDL berasaskan Tcl. | |
| Verilog | HDL yang paling meluas penggunaannya serta sokongannya | |
| VHDL | VHSIC HDL | HDL yang paling meluas penggunaannya serta sokongannya |
Rujukan [sunting]
- ↑ Eurich, J.P. and Roth, G. (1990): "EDIF grows up". IEEE Spectrum, Vol. 27, Issue 11, pp. 68 - 72.